1. Field of the Invention
The present invention relates to field programmable logic and interconnect architectures. More specifically, the present invention relates to a clock distribution architecture for use in field programmable interconnect architectures.
2. The Prior Art
Antifuse-based user programmable logic and interconnect architectures such as those manufactured by Actel Corporation of Sunnyvale, Calif. and disclosed in U.S. Pat. Nos. 4,758,745, 4,870,302, 4,910,417, and 5,055,718 are very useful circuit building blocks since they allow the user to configure a circuit as needed for a particular application. Other user-configurable architectures, such as the XC-4000 Series of Field Programmable Gate Array (FPGA) products manufactured by Xilinx, Inc., and the 7000 Series FPGA products manufactured by Altera Corporation are useful for the same general applications. Configuration of these circuits is performed by the user in his own environment using one of a number of different types of programmable interconnect elements. Architectures such as those noted above allow the configuration of both combinational and sequential circuits as needed. The function of the circuit elements and the required interconnected pattern to configure the circuit to the desired circuit application are simply programmed into the circuit.
A common problem encountered with architectures which employ this approach is the delay introduced into the circuit paths between logic circuit modules by the interconnect elements themselves. This delay is due to the resistance and capacitances associated with the interconnect element and architecture and has heretofore been accepted as the price to be paid for user programmability.
Masked gate arrays have significantly lower interconnect delays than do their user-programmable counterparts because the resistive and capacitive component of the interconnect is significantly smaller. The delays in the circuit and the propagation delays of the logic function unit modules themselves determine the overall speed or performance of the masked gate array application circuit.
Since typical application circuits in such architectures include sequential elements, such as flip-flops and latches, programmably connectable clocking capability is required to interconnect clocks to the clock inputs of each latch and flip flop in the circuit to correctly operate the sequential circuits. Typical application circuits require only a few clocks in the entire circuit which are common and shared by all sequential elements. Application circuits employing a single clock network providing for complementary system clocks, such as the Xilinx XC-4000 series FPGA and the Altera series of EPLDs, are known in the art.
Due to the interconnect delay inherent in general routing and interconnect and the need to avoid timing violations, clock networks must be handled separately and in a different manner than interconnect for other circuit networks. In order to minimize the inherent delay in clock distribution networks, some architectures, like the one employed by the Xilinx XC-4000 Series products and the Altera series of EPLDs, have employed dedicated clock distribution networks which do not contain any user-programmable elements in the clock paths.
Despite the existence of the above-named products and similar products, there remains room for improvement in the organization, speed and versatility of clock network architectures for use in user-programmable integrated circuit products.
It is an object of this invention to provide a clock distribution scheme which allows significantly higher circuit operating speeds than are permitted in prior art architectures.
It is another object of this invention to provide a clock distribution scheme which consumes less power than schemes in prior art architectures.
It is a further object of this invention to provide a clock distribution scheme which provides smaller clock skew within a net than in prior art architectures.
It is a further object of the present invention to provide a clock distribution scheme which is more versatile than prior art clock distribution schemes.